Registration

Welcome

Application-Specific Instruction-Set Processors: Bridging Flexibility and Efficiency

Break

Hardware-Aware Neural Architecture Search for Vision Models

LLM for Performance Simulator

Lunch

The Magic of Feedback (in Analog Circuit Design)

Harmonic Boosting in VCOs for THz Sensing

Break

Poster Pitches

Poster Session

Dinner & Icebreaker Session

Hardware Security Countermeasures against Side-channel Attacks for AES

Area-efficient, Digitally Controlled PLL Design with a novel TDC Architecture and Fast-locking

Break

Lunch

International Teamwork

International Teamwork

Break

Control Logic Design with noRTL

Break

City Tour

Bar Crawl (optional, at participant's own expense)

Energize your ICs with Power Management

Break

Moore's Law: Dead or Alive? Scaling Limits and the Promise of 3D Integration

Break

Analysis of Publicly Disclosed Vulnerabilities in FPGA IP Cores

Lunch

Open-Source Analog and Mixed-Signal IC Design Using ORDeC

Break

CMOS-MEMS Integration for Biomedical Applications

Midweek Celebration Dinner

Sponsor Keynote

New Motor Control Software-Architecture for future Software Defined Vehicle

Research & Innovation Exhibition

Lab & Cleanroom Tours

Lunch

Lab & Cleanroom Tours

Introduction into IHP's Open Source PDK and MPW

Gallium Nitride Technology and its role in Optical Neuromorphic Computing

Break

BBQ

FPGAs made in Germany

Break

Visit of the Einstein-Elevator

Lunch

Feedback

Graduation & Farewell